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    פורסם לפני
    2 שנים

    FPGA Design Engineer – student position (#0955)

    Ceragon
    Pazit Zaidenberg-Porat סטודנטים

    הערה: פג תוקף מודעה זאת, יתכן ואינה רלוונטית עוד. מעבר למשרות אחרונות

    תאור המשרה

    זמינות: משרה חלקית
    אזור: מרכז

    Job Description: • Logic design engineer that will join Ceragon Digital Solutions group • Taking part in the architecture and implementation of complex: Networking IPs, MAC layer and SoC design • Working closely with Ceragon system team developing together high end DSP and Networking IPs. • Responsible for the correctness and deployments of the IP • Communicating, when require, with external vendors Job Requirements: • 2nd/3rd year student of BSc in Computer science/ Electrical engineering from known University- Must. • Strong background in networking, communications protocols and/or signal processing – Must. • Experience as VLSI/FPGA Design Engineer with Verilog- Advantage. • Strong system understanding – Must • Experience with FPGA synthesis, timing closure and/or ASIC flow • FPGA and complex system debugging experience • Experienced in implementation of complex communication IP – Advantage. *The position applies for both men and women. Please send your CV+ Grads sheet

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    לשליחת קורות חיים - התחבר או הרשם

    קטגוריה: הייטק-חומרה. סוג המשרה: סטודנטים.



    Job Description: • Logic design engineer that will join Ceragon Digital Solutions group • Taking part in the architecture and implementation of complex: Networking IPs, MAC layer and SoC design • Working closely with Ceragon system team developing together high end DSP and Networking IPs. • Responsible for the correctness and deployments of the IP […]

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